km68fs8100 family preliminary revision 0.0 august 1999 1 cmos sram document title 1m x8 bit super low power and low voltage full cmos static ram revision history revision no. 0.0 remark preliminary history initial draft draft date august 25, 1999 the attached datasheets are provided by samsung electronics. samsung electronics co., ltd. reserve the right to change the speci fications and products. samsung electronics will answer to yourquestions about device. if you have any questions, please contact the samsung b ranch offices.
km68fs8100 family preliminary revision 0.0 august 1999 2 cmos sram 1m x 8 bit super low power and low voltage full cmos static ram general description the km68fs8100 families are fabricated by samsung s advanced full cmos process technology. the families support industrial operating temperature ranges and have chip scale package for user flexibility of system design. the families also support low data retention voltage for battery back-up operation with low data retention current. features process technology: full cmos organization: 1m x8 power supply voltage: 2.3~2.7v low data retention voltage: 1.5v(min) three state output and ttl compatible package type: 48-fbga-8.00x12.00 name function name function cs 1 , cs 2 chip select inputs a 0 ~a 19 address inputs oe output enable input vcc power we write enable input vss ground i/o 1 ~i/o 16 data inputs/outputs dnu do not use pro duct family 1. the parameter is measured with 30pf test load. product family operating temperature vcc range speed power dissipation pkg type standby (i sb1 , typ.) operating (i cc1 , max) km68fs8100i industrial(-40~85 c) 2.3~2.7v 70*/85ns 0.5 m a 3ma 48-fbga-8.00x12.00 samsung electronics co., ltd. reserves the right to change products and specifications without notice. functional block diagram pin description clk gen. row select i/o 1 ~i/o 8 data cont data cont vcc vss precharge circuit. memory array 2048 rows 256 8 columns i/o circuit column select we oe cs 1 control logic cs2 row addresses column addresses dnu oe a0 a1 a2 cs2 dnu dnu a3 a4 cs 1 dnu i/o1 dnu a5 a6 dnu i/o5 vss i/o2 a17 a7 i/o6 vcc vcc i/o3 v cc a16 i/o7 vss i/o4 dnu a14 a15 dnu i/o8 dnu dnu a12 a13 we dnu a18 a8 a9 a10 a11 a19 1 2 3 4 5 6 a b c d e f g h 48-fbga: top view (ball down)
km68fs8100 family preliminary revision 0.0 august 1999 3 cmos sram product list industrial temperature products(-40~85 c) part name function KM68FS8100FI-7 km68fs8100fi-8 48-fbga, 70ns, 2.5v 48-fbga, 85ns, 2.5v absolute maximum ratings 1) 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. functional oper ation should be restricted to recommended operating condition. exposure to absolute maximum rating conditions for extended periods may affect re liability. item symbol ratings unit voltage on any pin relative to vss v in ,v out -0.2 to 3.0 v voltage on vcc supply relative to vss v cc -0.2 to 3.6 v power dissipation p d 1.0 w storage temperature t stg -55 to 150 c operating temperature t a -40 to 85 c functional description 1. x means don t care. (must be low or high state) cs 1 cs 2 oe we i/o 1~8 mode power h x 1) x 1) x 1) high-z deselected standby x 1) l x 1) x 1) high-z deselected standby l h h h high-z output disabled active l h l h dout read active l h x 1) l din write active
km68fs8100 family preliminary revision 0.0 august 1999 4 cmos sram recommended dc operating conditions 1) note: 1. t a =-40 to 85 c, otherwise specified 2. overshoot: v cc +1.0v in case of pulse width 20ns. 3. undershoot: -1.0v in case of pulse width 20ns. 4. overshoot and undershoot are sampled, not 100% tested. item symbol min typ max unit supply voltage vcc 2.3 2.5 2.7 v ground vss 0 0 0 v input high voltage v ih 2.2 - vcc+0.2 2) v input low voltage v il -0.2 3) - 0.4 v capacitance 1) (f=1mhz, t a =25 c) 1. capacitance is sampled, not 100% tested item symbol test condition min max unit input capacitance c in v in =0v - 8 pf input/output capacitance c io v io =0v - 10 pf dc and operating characteristics 1. super low power product=10 m a with special handling. item symbol test conditions min typ max unit input leakage current i li v in =vss to vcc -1 - 1 m a output leakage current i lo cs 1 =v ih, cs 2 =v il or oe =v ih or we =v il , v io =vss to vcc -1 - 1 m a operating power supply current i cc i io =0ma, cs 1 =v il, cs 2 =v ih , we =v ih , v in =v ih or v il - - 2 ma average operating current i cc1 cycle time=1 m s, 100%duty, i io =0ma, cs 1 0.2v, cs 2 3 vcc-0.2v, v in 0.2v or v in 3 vcc-0.2v - - 2 ma i cc2 cycle time=min, i io =0ma, 100% duty, cs 1 =v il , cs 2 =v ih, vin=v il or v ih - - 25 ma output low voltage v ol i ol = 2.1ma 0.4 v output high voltage v oh i oh = -1.0ma 2.2 v standby current(ttl) i sb cs 1 =v ih , cs 2 =v il , other inputs=v ih or v il - - 0.3 ma standby current(cmos) i sb1 cs 1 3 vcc-0.2v, cs 2 3 vcc-0.2v( cs 1 controlled) or cs 2 0.2v(cs 2 controlled), other inputs=0~vcc - 0.5 20 1) m a
km68fs8100 family preliminary revision 0.0 august 1999 5 cmos sram ac operating conditions test conditions (test load and input/output reference) input pulse level: 0.2 to 2.2v input rising and falling time: 5ns input and output reference voltage:1.1v output load(see right): c l =100pf+1ttl c l =30pf+1ttl data retention characteristics 1. cs 1 3 vcc-0.2v,cs 2 3 vcc-0.2v( cs 1 controlled) or cs 2 3 vcc-0.2v(cs 2 controlled). 2. super low power product=4 m a with special handling. item symbol test condition min typ max unit vcc for data retention v dr cs 1 3 vcc-0.2v 1) 1.5 - 2.7 v data retention current i dr vcc=1.5v, cs 1 3 vcc-0.2v 1) - 0.5 6 2) m a data retention set-up time t sdr see data retention waveform 0 - - ms recovery time t rdr trc - - ac characteristics (vcc=2.3~2.7v, t a =-40 to 85 c) parameter list symbol speed bins units 70ns 85ns min max min max read read cycle time t rc 70 - 85 - ns address access time t aa - 70 - 85 ns chip select to output t co1 , t co2 - 70 - 85 ns output enable to valid output t oe - 35 - 40 ns chip select to low-z output t lz1 , t lz2 10 - 10 - ns output enable to low-z output t olz 5 - 5 - ns chip disable to high-z output t hz1 , t hz2 0 25 0 25 ns oe disable to high-z output t ohz 0 25 0 25 ns output hold from address change t oh 10 - 10 - ns write write cycle time t wc 70 - 85 - ns chip select to end of write t cw1 , t cw2 60 - 70 - ns address set-up time t as 0 - 0 - ns address valid to end of write t aw 60 - 70 - ns write pulse width t wp 50 - 60 - ns write recovery time t wr 0 - 0 - ns write to output high-z t whz 0 25 0 25 ns data to write time overlap t dw 25 - 35 - ns data hold from write time t dh 0 - 0 - ns end write to output low-z t ow 5 - 5 - ns c l 1) 1. including scope and jig capacitance r 2 2) r 1 2) v tm 3) 2. r 1 =3070 w , r 2 =3150 w 3. v tm =2.3v
km68fs8100 family preliminary revision 0.0 august 1999 6 cmos sram address data out previous data valid data valid timming diagrams timing waveform of read cycle(1) (address controlled , cs 1= oe =v il , cs2= we =v ih ) t aa t rc t oh timing waveform of read cycle(2) ( we =v ih ) data valid high-z cs 1 address oe data ou t notes ( read cycle) 1. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection. cs 2 t oh t aa t olz t lz t ohz t hz(1,2) t rc t co2 t oe t co1
km68fs8100 family preliminary revision 0.0 august 1999 7 cmos sram timing waveform of write cycle(1) ( we controlled) address cs 1 t cw(2) t wr(4) timing waveform of write cycle(2) ( cs 1 controlled) address cs 1 t wc t wr(4) t as(3) cs 2 t cw(2) t wp(1) t dw t dh t ow t whz data undefined data valid we data in data out t dw t dh data valid we data in data out high-z high-z cs 2 t wc t aw t as(3) t cw(2) t wp(1) t aw
km68fs8100 family preliminary revision 0.0 august 1999 8 cmos sram data retention wave form cs 1 controlled v cc 2.3v 2.0v v dr cs 1 gnd data retention mode cs 1 3 v cc - 0.2v t sdr t rdr timing waveform of write cycle(3) (cs 2 controlled) address cs 1 t aw notes (write cycle) 1. a write occurs during the overlap of a low cs 1 , a high cs 2 and a low we . a write begins at the latest transition among cs 1 goes low, cs 2 going high and we going low : a write end at the earliest transition among cs 1 going high, cs 2 going low and we going high, t wp is measured from the begining of write to the end of write. 2. t cw is measured from the cs 1 going low or cs 2 going high to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr1 applied in case a write ends as cs 1 or we going high t wr2 applied in case a write ends as cs 2 going to low. cs 2 t cw(2) we data in data valid data out high-z high-z t cw(2) t wr(4) t wp(1) t dw t dh t as(3) t wc cs 2 controlled v cc 2.3v 0.4v v dr cs 2 gnd data retention mode t sdr t rdr cs 2 0.2v
km68fs8100 family preliminary revision 0.0 august 1999 9 cmos sram c 1 / 2 package dimension 6 5 4 3 2 1 a b c d e f g h c b/2 b c 1 b c bottom view top view d e 2 e 1 e c side view 0 . 8 5 / t y p . 0 . 2 5 / t y p . a y detail a min typ max a - 0.75 - b 7.90 8.00 8.10 b1 - 3.75 - c 11.90 12.00 12.10 c1 - 5.25 - d 0.30 0.35 0.40 e - 1.10 1.20 e1 - 0.85 - e2 0.20 0.25 0.30 y - - 0.08 0.50 0.50 b1 #a1 0 . 3 0 a1 index mark notes. 1. bump counts: 48(8row x 6column) 2. bump pitch : (x,y)=(0.75 x 0.75)(typ.) 3. all tolerence are +/-0.050 unless otherwise specified. 4. typ : typical 5. y is coplanarity: 0.08(max) unit: millimeters 48 ball fine pitch bga(0.75mm ball pitch)
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